High Level Synthesis Methodology for Highly Testable and Nonzero Clock Skew Low Power Design
نویسندگان
چکیده
منابع مشابه
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization
The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits its smallest standby leakage current its power gating can achieve. In this paper, we point out that, in the high-level synthesis of a nonzero clock skew circuit, the resource binding (including functional...
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